module Mux4_8bit (
	input [1:0] sel,   
	input [7:0] in0,       
	input [7:0] in1,      
	input [7:0] in2,      
	input [7:0] in3,        
	output [7:0] out  
);

	genvar i;
	generate
		for (i = 0; i < 8; i = i + 1) begin : mux_per_bit
			Mux4to1_1bit m4 (
			.sel(sel),
			.a(in0[i]),
			.b(in1[i]),
			.c(in2[i]),
			.d(in3[i]),
			.out(out[i])
			);
		end
	endgenerate

endmodule


module Mux4to1_1bit (
	input [1:0] sel,
	input a,
	input b,
	input c,
	input d,
	output out
);
	assign out = (~sel[1] & ~sel[0] & a) |(~sel[1] &  sel[0] & b) |( sel[1] & ~sel[0] & c) |( sel[1] &  sel[0] & d);
endmodule
